`include "defines.v"
module pipelineControl(
  input rst_n,
  // flush request
  input ex_br_flush_i,
  input csr_commit_flush_i,
  // flush signal
  output ctrl_fronted_flush_o,
  output ctrl_idu_flush_o,
  output ctrl_isu_flush_o,
  output ctrl_exu_flush_o,
  output ctrl_wbu_flush_o,
  // 
  output ctrl_baq_flush_o
);

assign ctrl_fronted_flush_o  = csr_commit_flush_i || ex_br_flush_i;
assign ctrl_idu_flush_o      = csr_commit_flush_i || ex_br_flush_i; 
assign ctrl_isu_flush_o      = csr_commit_flush_i || ex_br_flush_i; 
assign ctrl_exu_flush_o      = csr_commit_flush_i || ex_br_flush_i;
assign ctrl_wbu_flush_o      = csr_commit_flush_i || 'd0;

assign ctrl_baq_flush_o      = ex_br_flush_i || csr_commit_flush_i;
endmodule